Design and Performance of Beam Test Electronics for the PHENIX Multiplicity Vertex Detector

The system architecture and test results of the custom circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode This paper presents measurements of the prototype circuits including the preamplifier-discriminator, analog memory unit ( M U ) , analog-digital converter (ADC) and heap manager for the MVD detector front-end electronics (FEE). The system was run in the BNL AGS facility as a fixed-target experiment. The electronics, however, were run as simultaneous read-write with a sampling rate of 400 ns. summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 ps ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 p n-well CMOS process used for preamplifier fabrication.